1. Field of the Invention
The present invention relates to a word line selection circuit that selects a word line of a semiconductor memory device, and to a row decoder.
2. Description of Related Art
Regarding a word line selection circuit of a semiconductor memory device, circuits are known such as those disclosed in Japanese Patent No. 3838892 and Japanese Unexamined Patent Application Publication No. H07-254275. A schematic configuration and an operation of the related semiconductor memory device will be explained with reference to FIGS. 12 and 13. In FIG. 12, address signals that select word lines are applied to terminals 21 to 23. An address buffer 26 buffers address signals A0 to A10 which are applied at different times to the terminals 21 to 23, and outputs the buffered address signals. A pre-decoder 30 is connected to the address buffer 26, decodes address data A0 and A1 to output them as a 4-bit signal SSD, decodes address data A2 to A9 in two bit groups in similar fashion to A0 and A1, and furthermore, outputs a signal AS generated by amplifying address data A10 and an inverted signal/AS thereof. Subsequently, a main decoder 60 is connected to the pre-decoder 30, and receives the outputs generated by decoding the address data A2 to A9. The main decoder 60 further decodes the outputs from the pre-decoder 30, and supplies them to first word decoders 70 and 80. The first word decoders select a word line MWL of a memory cell array based on the outputs of the main decoder 60, and then activate it.
Here, the first word decoders 70 and 80 are composed of sub-decoders 71 to 84. FIG. 13 shows a configuration of the sub-decoder. As shown in FIG. 13, the sub-decoder is provided with 64 three-input NAND gates NG0 to NG63 and drivers DV0 to DV63 that perform level conversion and amplification of outputs of the respective NAND gates NG0 to NG63.
Each of the drivers DV0 to DV63 are, as shown in FIG. 13, is composed of a level conversion circuit 131, P channel FET 132, and N channel FET 133. An output of the level conversion circuit 131 is applied to each gate of the FETs 132 and 133. A boosted boost voltage Vbt is supplied to the level conversion circuit B1 and to a source of the FET 132. Drains of the FETs 132 and 133 are connected to each other, and a source of the FET 133 is grounded. According to such a configuration, the driver circuits DV0 to DV63 output the boosted voltage Vbt when the outputs of the NAND gates NG0 to NG63 are “0”, while they output a ground potential when they are “1.”
However, in an inverter circuit in which a high voltage is applied to the source of the P channel FET as shown in FIG. 13, as described in Japanese Unexamined Patent Application Publication No. H07-254275 (paragraph 0004), a control signal input into a common gate of an inverting buffer needs to be a control signal of VPP (the H level of the control signal is VPP) (Note that a boosted VPP described herein is synonymous with the aforementioned boost voltage Vbt.)
The reason is that in a case where the PMOSFET 132 is controlled by a control signal of VCC (the H level of the control signal is the VCC), when the H level (VCC) is input into the gate, there occurs a disadvantage that the PMOSFET 132 is not completely turned off since the source voltage is the VPP. Hence, a signal that controls the gate of the PMOSFET needs to be the control signal of the VPP, but since the outputs of the decoder are control signals of the VCC, it is necessary to convert a signal level from the VCC into the VPP. For this reason, it is necessary to provide a level conversion circuit between a row decoder and the PMOSFET.
However, since a level conversion circuit should be provided for each word line in the configurations shown in FIGS. 12 and 13, a number of level conversion circuits are needed. If the level conversion circuits are provided in addition to a decoder logic as described above, the number of transistors substantially increases, thus leading to the increase in an area of the word line selection circuit. Further, in order to provide the level conversion circuit for every word line, the level conversion circuits must be arranged by a cell pitch of memory cells in view of a chip layout. In addition, the number of circuit stages increases along with that of the level conversion circuits provided between the decoder logic and the inverting buffer, thus preventing the speed-up of the circuit.
Here, if the level conversion circuits are arranged at a preceding stage to the row decoder, and the decoded signals themselves are made into boosted signals, the number of the level conversion circuits can be reduced. However, the larger becomes areas of the circuits driven by signals with large amplitude, the more power consumption increases.
It is to be noted that Japanese Unexamined Patent Application Publication No. H07-254275 discloses a configuration that among precharge signals and groups of address signals that control a row decoder, a level of only the precharge signals is converted to VPP and then they are input into the row decoder (FIGS. 1 and 2, and paragraph 0039 of Japanese Unexamined Patent Application Publication No. H07-254275). This configuration is shown in FIG. 14. Namely, a PMOSFET 14, whose drain is connected to a word line WL and whose source is to a boosted potential VPP, is provided at a row decoder 13 of a word line selection circuit 16. Only a precharge signal PRCH′ that controls a gate of this PMOSFET 14 is then made into a boosted signal. Meanwhile, the groups of the address signals applied to gates of other FETs that constitute a decode logic (NAND gate) 15 of the row decoder 13 are held as VCC.
In the aforementioned configuration, level conversion is performed only to a control signal PRCH for precharge supplied to the gate of the PMOSFET 14 among the signals that control the row decoder 13, and then the PRCH is made into the control signal PRCII′ of the VPP. This is because the control signal that controls an NMOSFET necessarily need not supply the control signal of the VPP although the control signal that controls the PMOSFET 14 certainly needs to be the control signal of the VPP. Namely, this is because if trying to control the PMOSFET 14 with the control signal of the VCC, the transistor is not completely turned off when the control signal is at the II level (VCC level). On the other hand, controlling the NMOSFET with the control signal of the VCC, the transistor is completely turned off when the control signal is at an L level (VSS level), so that there is no disadvantage in a circuit operation. Note that if the control signal of the NMOSFET is the control signal of the VPP, there is no problem in the circuit operation. According to this configuration, it is not necessary to provide the level conversion circuit for every row decoder 13, thus enabling to reduce the number of the level conversion circuits.